The present invention relates generally to the field of three dimensional (3D) graphics processing, and more particularly to efficient parametric surface binning based on control points.
Three dimensional or 3D objects are typically represented on computer display screens as being composed of graphics primitives such as triangle lists, triangle strips, and triangle fans. The graphics primitives are defined by a host computer or a graphics processor in terms of primitive data. For instance, the three vertices of each triangle in a primitive are defined in terms of its spatial location with X, Y, and Z coordinates. Additional data defines the red, green, and blue (RGB) color values and texture coordinates of each vertex. Other primitive data can be included depending on each specific application. Rendering hardware processes the primitive data to activate display screen pixels that compose each primitive and the RGB color values for each pixel.
A technique called xe2x80x9ctilingxe2x80x9d (or chunking, as some literature""s naming convention) is often used to improve the memory bandwidth required for rendering the graphics primitives. In this scheme, the display screen is partitioned into tiles (or bins as in the naming convention of some literature) that span the display screen. Each tile is rendered independently of the others by the graphics processor or host computer. With the help of tile sized caches that retain the color (RGB) and depth data of a tile, memory bandwidth can be reduced dramatically. This improves graphics processing performance since 3D graphics processing is most often limited by the available memory bandwidth in the computer system.
Tiling involves the sorting of graphics primitives into bins or tiles. FIGS. 1A and 1B show an example of sorting graphics primitives into bins or tiles. FIG. 1A is a diagram depicting several 3D objects arranged on a display screen 100 in accordance with prior art systems. The display screen 100 is partitioned into four rectangular tiles (or bins) 110, 120, 130, and 140. In this example, 3D primitives 160, 170, and 180 are received by a processor. The processor sorts the 3D primitives 160, 170, 180 into bins 110, 120, 130, 140. Although this example describes the screen area as divided into only four bins, other embodiments can have the screen divided into any of a wide range of numbers or shapes of bins. Typically, the number of bins would greatly exceed four. After receiving data for a graphics primitive, the processor determines which bin or tile the primitive intersects. The sorting of graphic primitives to the bins that the primitives intersect is hence called binning.
FIG. 1B is a diagram depicting the several objects of FIG. 1A sorted into bins. For example, the processor determines that the 3D primitive 160 is located partially within bin 110 and partially within bin 120. The processor then delivers copies of the various primitives to the graphics memory storage areas for whatever bins the primitives intersect. Here, the processor would deliver copies of the primitive data for 3D primitive 160 to the graphics memory storage area for bins 110 and 120. Another 3D primitive 170 is located within bin 110, within bin 130, and within bin 140. Similarly, 3D primitive 180 is located within bin 120 and bin 130. The data for the other objects are also stored accordingly.
Once the 3D primitives 160, 170, 180 are sorted into bins, a graphics processor reads the data for each bin on a bin-by-bin basis and divides the larger primitives into smaller primitives that fit within each tile. For example, 3D primitive 160 is divided by the graphics processor to create primitive 161 within bin 110 and primitive 162 within bin 120. The 3D primitive 170 is divided by the graphics processor to create primitive 171 within bin 110, primitive 173 within bin 130, and primitive 174 within bin 140. The 3D primitive 180 is divided by the graphics processor to create primitive 182 within bin 120 and primitive 183 within bin 130. The divided 3D primitives are then delivered to drawing and rendering engines on a bin-by-bin basis.
FIG. 2 is a flow diagram of a prior art method for handling parametric surfaces in a tiled graphics architecture. At step 202, the processor receives a scene which consists of multiple parametric surfaces. The scene is processed by rendering all of the parametric surfaces in the scene. Each parametric surface is received from the scene at step 204. Tessellation of the parametric surface occurs at step 206. Tessellation is the process of converting the parametric surfaces into 3D primitives. At step 208, each 3D primitive is sorted and binned. The processor checks at step 210 whether additional surfaces are present in the scene and still have to be processed. If there are more surfaces, the process repeats at step 204. If there are no more surfaces for processing, the scene is done.
There is a growing trend towards using parametric surfaces as the basis for 3D graphics rendering. However the prior art of converting parametric surfaces into 3D primitives increases the amount of data to be transferred to graphics processors. In a tiled graphic architecture, this increase is amplified by the need to duplicate each 3D primitive to each and every bin the primitive intersects. The bandwidth increase due to tessellation and binning can adversely affect the bandwidth saving advantage of tiling. Hence a technique for efficient binning of these parametric surfaces is desirable.